TSMC certified Cadence digital design workflows for the latest N3E and N4P processes
Cadence Design Systems, Inc. (for more information about the company click who) based in San Jose, California, is an American multinational computing software company, founded in 1988. Today, it announced that its digital and custom / analog design streams have been certified for TSMC processes N3E and N4P. Supporting the latest Design Rule Manual (DRM). Furthermore, Cadence e TSMC provided N3E and N4P process design kits (PDKs) and design flows to accelerate customer adoption. In order to promote innovation in mobile computer design, IA e hyperscale.
Joint customers are actively planning with new ones PDK N3E and N4P and several test chips have already been eliminated. Which demonstrates how Cadence solutions help customers improve engineering efficiency, maximize power benefits and performance. Cadence solutions for advanced digital nodes and custom / analog support the company’s intelligent systems design strategy. This enables excellence in system-on-chip design (SoC).
Cadence worked closely with TSMC to ensure that the complete digital flow was optimized for advanced process technologies N3E e N4P by TSMC. The complete flow from RTL a GDS includes various implementation systems. Among these we have Cadence Innovus, How Much Extraction Solution, How Much Field Solver, Tempus Timing Signoff Solutionand option ECO. And again Pegasus Verification System, Liberate Characterization Solution e Voltus IC Power Integrity Solution. In addition, the Cadence Genus Synthesis Solution and technology iSpatial predictive have been enabled for TSMC N3E and N4P process technologies.
The complete digital stream offers several key functionality which support TSMC N3E and N4P process technologies. Among these we have the correlation between implementation and the results of approval and enhancement through the support of the pillar. Furthermore, you will have an efficient management of large standard cell libraries containing many cells multi-heightvoltage threshold (VT) and drive power. Finally, low voltage cell characterization, certified timing accuracy and certified extraction accuracy with How Much Extraction Solution e How Much Field Solver.
The Cadence Virtuoso Design Platformwhich includes Virtuoso Schematic Editor, Virtuoso ADE Product Suite and Virtuoso Layout Suite EXL, the Specter Simulation Platform, obtained the latest TSMC N3E and N4P certifications. A unique capability offered by the Virtuoso design platform is the tight integration with the implementation system Innovus. This improves the implementation methodology of mixed-signal projects using a common database. The Virtuoso Schematic Editor migration module in the Virtuoso application library environment has been integrated and verified by TSMC.
The Virtuoso Schematic Editor, the Virtuoso ADE Suite and the simulator Spectre X integrated, have been optimized for the custom design reference flow (CDRF). This is used for the management of corner simulations, statistical analyzes, project centering and circuit optimization. In addition, the Virtuoso Layout Suite EXL of CDRF has been enhanced for efficient layout implementation, which provides customers with several features. Among these stands out a unique implementation methodology based on lines with interactive and assisted functions for positioning, routing, filling and dummy insertion. We also have an improved analog migration and layout reuse functionality. Finally, don’t forget the integrated parasitic extraction and controls IN GO with built-in physical verification capabilities.
Below are some statements about the new Candice digital design flows.
Thanks to our latest partnership with Cadence, we are making it easy for customers to benefit from the significant increases in power and performance of our latest N3E and N4P process technologies,
he has declared Suk Leevice president of Design Infrastructure Divisione management at TSMC. Then adding
Our clients have to develop projects at an exceptionally fast pace to keep up with market demands. Design flow certification gives customers the confidence that they can use our technologies to achieve their design goals and get to market faster.
Furthermore, Dr. Chin-Chi Tengsenior vice president and general manager of digital and endorsement group at Cadence, states that:
Our digital and custom / analog streams are feature-rich that enable our customers to achieve an optimal PPA. At the same time, it improves engineering productivity when creating N3E and N4P projects.
By working closely with TSMC, we are helping customers achieve SoC design excellence in a variety of market segments such as
And what do you think of these new ones Candice digital design streams? tell us yours below in the comments and stay connected on TechGameWorld.com, for the latest news from the world of technology (and more!).
The article Cadence Digital Design Streams: Certified by TSMC comes from TechGameWorld.com.
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