Intel presents its new mobile processor “Meteor Lake-P” with 6P + 8E Compute Tile
The mobile processor “Meteor Lake-P“New generation of Intel (for more information about the company click here) with a Compute Tile 6P+8E was presented to 2022 IEEE VLSI Symposium on Tech and Circuits . The new mobile processor possesses 6 high performance cores and 8 efficiency cores. We now have annotations for all four panes, as well as a close-up of the calculation pane. Intel has also confirmed that Compute Tile will be built on its manufacturing process with intel 4 homebrew silicon. This offers an increase in iso-power performance of over 20% compared to the Intel 7 nodethrough extensive use of EUV lithography.
The upgrade of the new Meteor Lake-P mobile processor
We had previously seen a version 2P+8E del Compute Tile “Meteor Lake”, probably from the “Meteor Lake-U” package. The larger 6P + 8E processing panel features six “Redwood Cove” performance cores and two “Crestmont” efficiency core clusters, each with four E-cores. Assuming the L3 cache portion for P-core or E-core cluster is 2.5MB, they must be present 20 MB of L3 cache on the calculation pane. Each P-core has 2 MB of dedicated L2 cachewhile each of the two E-core clusters shares 4 MB of L2 cache between four E-cores.
Let’s see the other three tiles: the tile iGPU (nicknamed GFX Tile), the tile SoC and the card I / O. The GFX Tile packs the iGPU, which is perhaps a more energy-dense component than even a P-core. So this tile most likely gets the most advanced silicon fabrication node on the pack, which is most likely the TSMC N3 (3 nm). The Tile SoC packs uncore and high-bandwidth I / O components, including memory controllers, the root complex PCI-Express 5.0the management engine, etc.
The I / O Tile is essentially a Integrated PCH that manages the I / O of the platform which does not have as heavy bandwidth as the main PEG interface or the main NVMe Gen 5 interface. This tile could be built with the less advanced manufacturing process. All four tiles are placed on a silicon interposer through Foveros 3D technology. The interposer is a silicon die that facilitates microscopic high-density wiring between the dies in a multi-chip module. This appears as a single die contiguous to the fiberglass substrate.
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