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Rialto Bridge GPU: the novelty of Intel

The Intel company has announced the new “Rialto Bridge” GPU from the Intel data center

During the International Supercomputing Conference in Hamburg, Intel unveiled the new GPU “Rialto Bridge” of Intel’s data center. Jeff McVeigh, vice president and general manager of Intel Corporation’s Super Compute Group, announced the new graphics processing unit. This will use the same architecture as the data center GPU Intel Ponte Vecchio. But it will also contain new updates, to offer up to 160 cores Xemore I / O bandwidth and limits Higher TDPs for higher density and performance.

Intel’s goals

This year, Intel (for more information on the company click here) is committed to achieving theelimination of net greenhouse gas emissions of its global operations by 2040. In addition, it will focus on developing more technology solutions sustainable.

As we embark on the era ofexascale and scroll to zettascalethe contribution of the technology industry to global carbon emissions is also growing. It has been estimated that by 2030, between 3% and 7% of global energy production will be consumed by data center with the IT infrastructure that will be one of the main drivers of the new use of electricity

Said Jeff McVeigh, vice president and general manager of the Super Compute Group di Intel Corporation. The goal is to keep up with the insatiable demands for processing while creating a sustainable future. This is one of the biggest challenges for high performance computing (HPC).

HPC

We have one roadmap HPC aggressive, planned until 2024 which will provide a diversified portfolio of heterogeneous architectures. These architectures will allow us to improve the performance. At the same time they will reduce the energy demand for both generic and emerging workloads such asartificial intelligencethe cryptography and theanalyses.

Intel Xeon

The processor Intel Xeon (codenamed Sapphire Rapids), with memory HBM (High Bandwidth Memory) is a great example of how we are leveraging advanced packaging technologies and silicon innovations. This is to make substantial improvements in performance, bandwidth and power savings for HPC. With a maximum of 64 gigabytes of HBM2E memory with high bandwidth in the package and accelerators built into the CPU, we will be able to have significant performance benefits in key HPC use cases.

Comparing 3rd Generation Intel Xeon Scalable processors to upcoming processors Sapphire Rapids HBMwe observe a performance increase two to three times in meteorological research, energy, production and physics workloads. At the keynote, Ansys CTO Prith Banerjee also showed that Sapphire Rapids HBM offers a performance boost up to 2 times higher on real Ansys Fluent and ParSeNet workloads.

Processing density

The processing density is another imperative as you try to achieve performance improvements in supercomputing workloads HPC and AI. Intel’s first flagship data center graphics processing unit (GPU) (codenamed Ponte Vecchio), already stands outclassing the competition. in the dress of aapplications of complex financial services and AI inference and training workloads. Intel also shows that Ponte Vecchio is accelerating the high-fidelity simulation of 2 times with OpenMC.

The improvements of the Rialto Bridge GPU

Intel didn’t stop at these great results, surprising everyone with the announcement of this powerful data center GPU, codenamed Rialto Bridge. This is based on the evolution of the Ponte Vecchio architecture and the combination of improved tiles with the technology of the next process node. Thus Rialto Bridge will offer significantly higher density, performance and efficiency, while providing software consistency.

Looking at the future, Falcon Shores is the next major architectural innovation on our roadmap, bringing architectures together X86 CPU and Xe GPU in one socket. This architecture is planned for the 2024 and plans to offer benefits of over 5 times the performance per watt, 5 times the processing density, 5 times the memory capacity and bandwidth improvements.

OneAPI

The industry initiative oneAPI provides developers HPC programming across architectures, so that code can be routed to CPUs, GPUs, and other specialized accelerators, transparently and portable. There are now more than 20 oneAPI centers of excellence at leading academic and research institutions around the world. These are making significant progress, such as Simon MacIntosh-Smith and his team at the Science Department of the University of Bristol. The team is developing best practices for achieving portability of performance at scale exa using oneAPI e energy efficiency. In the I / O 500 results for Luster, DAMAGE got an increase of 70 times the performance hard write file system.

Addressing the challenge of sustainability

Intel is proud to partner with like-minded customers to achieve a More sustainable HPC It’s open. Recent examples include partnering with the Barcelona Supercomputing Center to create a pioneering laboratory zettascale RISC-V. Or again, the continuous collaboration with theCambridge and Dell Universities to transform the current Exascale Lab in the new Cambridge Zettascale Lab. These efforts rely on plans to create a solid EU innovation ecosystem for the future of computing.

The bottom line is that no single company can do it alone. The whole ecosystem must lean the same way, including manufacturing, silicon, interconnection, software and systems. By doing this together, you can turn one of HPC’s greatest challenges into the opportunity of the century and change the world for future generations.

And what do you think of this new GPU Rialto Bridge and the new HPC? Let us know below in the comments and keep following us on TechGameWorld.com, to stay up to date with the latest news from the world of technology (and not only!).

The article GPU Rialto Bridge: the novelty of the Intel house comes from TechGameWorld.com.

Published by
Clare Hurwood

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